Title :
Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions
Author_Institution :
Dept. of Electr. & Comput. Eng., Singapore Nat. Univ.
Abstract :
Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling
Keywords :
MOSFET; hole mobility; internal stresses; semiconductor device reliability; CMOS transistor performance; channel orientation; lattice-mismatched materials; lattice-mismatched source-drain; source-drain regions; strain engineering; surface orientation; Capacitive sensors; Compressive stress; Germanium silicon alloys; Lattices; MOSFETs; Semiconductor materials; Silicon carbide; Silicon compounds; Silicon germanium; Tensile stress;
Conference_Titel :
SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International
Conference_Location :
Princeton, NJ
Print_ISBN :
1-4244-0461-4
DOI :
10.1109/ISTDM.2006.246557
