Title :
SiGe HBT design for CMOS compatible SOI
Author :
Chantre, Alain ; Avenier, G. ; Chevalier, P. ; Vandelle, B. ; Saguin, F. ; Maneux, Cristell ; Dutartre, D. ; Zimmer, T.
Author_Institution :
STMicroelectronics, Crolles
Abstract :
In this paper, we review the process and layout optimization of thin-film (150nm) SOI SiGe HBTs covering a wide range of fT-BVceo tradeoffs, i.e. from ~150GHz fT to ~8V BVceo. We have shown that a SiGe HBT with bulk-like fT-BVceo trade-off can be built on a CMOS compatible SOI substrate. This HBT can be modularly integrated at low cost (4 masks, < 30 steps) in a 0.13 mum SOI CMOS process (Boissonnet et al.). Anticipated applications range from wireless to high-speed analog circuitry
Keywords :
Ge-Si alloys; heterojunction bipolar transistors; semiconductor thin films; silicon-on-insulator; 0.13 micron; 150 nm; CMOS compatible SOI substrate; HBT design; SOI CMOS process; SOI thin film; SiGe; layout optimization; process optimization; CMOS technology; Doping profiles; Electrons; Germanium silicon alloys; Heterojunction bipolar transistors; Semiconductor films; Silicon germanium; Substrates; Thermal resistance; Virtual colonoscopy;
Conference_Titel :
SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International
Conference_Location :
Princeton, NJ
Print_ISBN :
1-4244-0461-4
DOI :
10.1109/ISTDM.2006.246558
