A Steiner tree construction for VLSI routing

Proposes a parallel, analog approach for the construction of a minimum rectilinear Steiner tree (MRST), which intuitively shrinks a bubble around the pins of the signal net until a Steiner tree topology is induced. This method maps well to parallel neural-style architectures, as well as to fairly generic two-dimensional array topologies. The author describes the basic approach along with extensive preliminary simulation results which show better performance than existing MRST approaches (i.e., almost 10% average improvement over minimum spanning tree cost). The result is of practical interest for VLSI CAD applications, and is an instance where an analog heuristic for an NP-complete problem outperforms existing combinatorial methods, both in time complexity and average-case performance