An analog neural network processor and its application to high-speed character recognition

Author

Boser, Bernhard E. ; Säckinger, Eduard ; Bromley, Jane ; Lecun, Yann ; Howard, Richard E. ; Jackel, Lawrence D.

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

Volume

i

fYear

1991

fDate

8-14 Jul 1991

Firstpage

415

Abstract

A high-speed programmable neural network chip and its application to character recognition are described. A network with over 130000 connections has been implemented on a single chip and operates at a rate of over 1000 classifications per second. The chip performs up to 2000 multiplications and additions simultaneously. Its datapath is suitable for the convolutional architectures that are typical in pattern classification networks, but can also be configured for fully connected or feedback topologies. Computations were performed with 6 bits accuracy for the weights and 3 bits for the states. The chip uses analog processing internally for higher density and reduced power dissipation, but all input/output is digital to simplify system integration

Keywords

CMOS integrated circuits; analogue computer circuits; character recognition; computerised pattern recognition; neural nets; additions; analog neural network processor; analog processing; character recognition; classifications per second; connections; convolutional architectures; datapath; digital input/output; multiplications; pattern classification networks; programmable neural network chip; states; weights; Character recognition; Computer networks; Intelligent networks; Network topology; Neural network hardware; Neural networks; Neurons; Pattern classification; Power dissipation; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 1991., IJCNN-91-Seattle International Joint Conference on

Conference_Location

Seattle, WA

Print_ISBN

0-7803-0164-1

Type

conf

DOI

10.1109/IJCNN.1991.155214

Filename

155214