Analog programmable chips for implementing ANNs using capacitive weight storage

The design approach for fully multiplexed 32×32 and 128×64 programmable analog vector-matrix multipliers utilizing capacitive weight storage is described. A fully differential design has been used throughout the signal path for cancellation of common-mode noise feedthroughs and reduction of multiplier and multiplexer offsets. The 32×32 vector-matrix multiplier circuit has been fabricated using the MOSIS 2-μm P-well CMOS technology. A method to increase dynamic range and a method to reduce power dissipation by an order of magnitude are described. Results showing operation of the 32×32 vector-matrix multiplier circuit are reported