An adaptive CMOS matrix-vector multiplier for large scale analog hardware neural network applications

The authors present an analog four-quadrant matrix-vector multiplier of low circuit complexity in floating gate CMOS technology, capable of on-chip weight adaptation following an arbitrary incremental outer-product local learning scheme, and with permanent storage of the weights after learning is performed. The complete adaptive circuit employs, on average, as few as two transistors per matrix element (C.F. Neugenbauer et al., 1990), allowing a very compact VLSI circuit layout (less than 30 μm×30 μm per synapse in standard 2 μm CMOS technology) suitable for the use in fully interconnected neural network hardware of densities above 256 neurons per cm². With proper biasing techniques, an input linearity region for the multiplier ranging 800 mV at modest current levels are demonstrated. Four-quadrant outer-product weight adaptation, performed locally on-chip by floating gate voltage increments under ultraviolet illumination, has been achieved with floating gate adaptation up to 10 mV/s