FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation

Computations in Support Vector Machines (SVM) involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation. The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.