• DocumentCode
    2767193
  • Title

    A Fully CMOS Low-Cost Chaotic Neural Network

  • Author

    Rosselló, José L. ; Bota, Sebastiá ; Canals, Vicens ; De Paul, Iván ; Segura, Jaume

  • Author_Institution
    Univ. de les Illes Balears, Palma de Mallorca
  • fYear
    0
  • fDate
    0-0 0
  • Firstpage
    659
  • Lastpage
    663
  • Abstract
    A chaotic IC is proposed and fabricated using a 0.35 mum CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 times 57 mum2), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.
  • Keywords
    CMOS integrated circuits; MOSFET; chaos; neural nets; random number generation; CMOS; MOS transistors; N-shaped transfer function; chaotic IC; low-cost chaotic neural network; neurons network; random number generator; CMOS integrated circuits; CMOS technology; Chaos; Chaotic communication; Circuit testing; Neural networks; Neurons; Operational amplifiers; Random number generation; Resistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 2006. IJCNN '06. International Joint Conference on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    0-7803-9490-9
  • Type

    conf

  • DOI
    10.1109/IJCNN.2006.246746
  • Filename
    1716157
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2767193