Title :
An efficient algorithm for irregular Low density Parity Check code with reduced computational complexity and error floor
Author :
Rathod, Devichand P. ; Awale, Raval N.
Author_Institution :
Dept. of Electron. Eng., VJIT, Mumbai, India
Abstract :
Low-density Parity check codes (LDPC) are gaining interest for high data rate application in both terrestrial and spatial communications which requires low bit error rate. This paper proposes an algorithm through which the best parity check matrix is obtained for irregular low density parity check codes, which reduces the Bit Error Rate ,Frame Error Rate and computational complexity. Tanner graph also called a bipartite graph format in an Low Density Parity Check (LDPC) code design contains many short cycles; it will produce a computational complexity in a code design process and it degrades the code performance. To overcome this effect, we proposed an new algorithm which obtains a best final parity check matrix. Throughout the paper we will give the detailed description of an efficient algorithm proposed. The complexity is studied graphically and analytically. Using proposed algorithm, cycles of length four observed in corresponding matrix are removed. Each matrix is evaluated over a noisy Additive White Gaussian Noise (AWGN) channel. Bit Error rate and Frame error rate is calculated. The results are compared with randomly generated best parity check matrix. Simulation results shows that proposed method successfully overcomes the computational complexity and meets the near Shannon limit.
Keywords :
AWGN channels; computational complexity; error statistics; parity check codes; AWGN channel; LDPC; Shannon limit; additive white Gaussian noise; bit error rate; code design process; computational complexity; error floor; frame error rate; high data rate application; irregular low density parity check code; parity check matrix; spatial communications; terrestial communications; Algorithm design and analysis; Bit error rate; Computational complexity; Encoding; Floors; Parity check codes; BPSk modulation; Irregular LDPC code; efficient algorithm; short cycles;
Conference_Titel :
Communication, Information & Computing Technology (ICCICT), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4577-2077-2
DOI :
10.1109/ICCICT.2012.6398190