• DocumentCode
    2768027
  • Title

    2003 IEEE International Integrated Reliability Workshop Final Report (IEEE Cat. No.03TH8715)

  • fYear
    2003
  • fDate
    23-23 Oct. 2003
  • Abstract
    The following topics are dealt with: interface traps, oxide traps, NBTI, PBTI, advanced CMOS, corona charging, thermal structures, gate oxide, reliability parameters, stress testing, dielectric thin films, charge trapping, MOCVD, stack structures, NPN, transistors, DC device, current mirror method, thermal instability, SOI, BJT, hot carrier, MOSFET, DPN, gate dielectrics, BiCMOS, PMOS, failure mode, SRAM, leakage current, circuit-level stress, inverter, copper dual-damascene interconnect, metal insulator metal capacitors, MIMCAP, memory chips, space applications, tunnel dielectric, ramped current, voltage, DRAM technology, GOI test, plasma charging, power pins, product screening stress, TDDB, HC measurements, PLDD, implant energy optimization, negative bias temperature instability, junction temperature, microelectronic device, dielectric barriers, joule heating, electromigration parameters, aluminium backend, oxide breakdown, magnetoresistive random access memory, MRAM, and product wafers.
  • Keywords
    BiCMOS integrated circuits; CMOS integrated circuits; chemical vapour deposition; electromigration; integrated circuit reliability; interface states; semiconductor device reliability; BJT; BiCMOS; DC device; DPN; DRAM technology; GOI test; HC measurements; MIMCAP; MOCVD; MOSFET; MRAM; NBTI; NPN transistors; PBTI; PLDD; PMOS; SOI; SRAM; TDDB; aluminium backend; charge trapping; circuit-level stress; copper dual-damascene interconnect; corona charging; current mirror method; dielectric barriers; dielectric thin films; electromigration parameters; failure mode; gate dielectrics; gate oxide; hot carrier; implant energy optimization; interface traps; inverter; joule heating; junction temperature; leakage current; magnetoresistive random access memory; memory chips; metal insulator metal capacitors; microelectronic device; negative bias temperature instability; oxide breakdown; oxide traps; plasma charging; power pins; product screening stress; product wafers; ramped current; reliability parameters; space applications; stack structures; stress testing; thermal instability; thermal structures; tunnel dielectric; voltage; BiCMOS integrated circuits; CMOS integrated circuits; CVD; Electromigration; Integrated circuit reliability; Interface phenomena; Semiconductor device reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Reliability Workshop Final Report, 2003 IEEE International
  • Conference_Location
    Lake Tahoe, CA, USA
  • Print_ISBN
    0-7803-8157-2
  • Type

    conf

  • DOI
    10.1109/IRWS.2003.1283288
  • Filename
    1283288