Title :
PMOS NBTI-induced circuit mismatch in advanced technologies
Author :
Agostinelli, M. ; Lau, S. ; Pae, S. ; Marzolf, P. ; Muthali, H. ; Jacobs, S.
Author_Institution :
Technol. Dev., Intel Corp., Hiilsboro, OR, USA
Abstract :
PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90 nm technology.
Keywords :
CMOS analogue integrated circuits; integrated circuit testing; 90 nm technology; CMOS technologies; NBTI; PMOS transistor degradation; analog applications; analog circuits; Analog circuits; CMOS technology; Circuit testing; Degradation; MOS devices; Niobium compounds; Operational amplifiers; Stress; Threshold voltage; Titanium compounds;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2003 IEEE International
Print_ISBN :
0-7803-8157-2
DOI :
10.1109/IRWS.2003.1283292
