Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression

A new, reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.264, WMV-9 andAVS. This is based on and extends a specific variable block-size architecture that we present for H.264 applications. The architecture exhibits simpler control, high throughput and relative low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high end video processing applications such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.