Analysis of a Fully-Scalable Digital Fractional Clock Divider

It was previously shown [5] that the BRESENHAM algorithm [2] is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal approximation of a desired clock in terms of the edges provided by the reference clock. Moreover, some synthesis results for hardwired dividers on Altera FPGAs showed that this technique for clock division achieves a high performance often at or close to the maximum frequency supported by the devices for moderate bit widths of up to 16 bits. This paper extends the investigations on the clock division by the BRESENHAM algorithm. It draws out the limits encountered by the existing implementation for both FPGA and VLSI realizations. A rather unconventional adoption of the carry-save representation combined with a soft-threshold comparison is proposed to circumvent these limitations. The resulting design is described and evaluated. Mathematically appealing results on the quality of the approximation achieved by this approach are presented.