Title :
Latch-up failure path between power pins in the mixed-voltage process
Author :
Wu, Chau-Neng ; Chou, H.-M. ; Chang, Michang
Author_Institution :
Taiwan Semicond. Manuf. Co., San Jose, CA, USA
Abstract :
A new latch-up failure phenomenon induced by the parasitic P-N-P-N path between power pins is reported here. This latch-up failure is observed in 0.13μm and 0.18μm process, but the test passes in 0.25μm. a traditional latch-up prevention methodology of guide-ring insertion works well here, and the chip is tape-out.
Keywords :
CMOS analogue integrated circuits; failure analysis; power supply circuits; semiconductor device reliability; semiconductor doping; guide-ring insertion; latch-up failure path; latch-up failure phenomenon; latch-up prevention methodology; mixed-voltage process; nanotechnology; parasitic P-N-P-N path; power pins; CMOS integrated circuits; CMOS process; CMOS technology; Equivalent circuits; MOSFETs; Pins; Process design; Semiconductor device manufacture; Variable structure systems; Voltage;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2003 IEEE International
Print_ISBN :
0-7803-8157-2
DOI :
10.1109/IRWS.2003.1283313
