Novel architecture implements a 1-GFLOP QR systolic processor

The authors consider the design, manufacture, and testing of an EPROM based DSP board, a prototype tri-port memory system and a dual port RAM module. A triangular systolic array is presented which provides a cost effective way of achieving a least squares optimising function in real time at audio rates. Its scaleability and speed renders it applicable to a large number of different linear signal processing tasks, not solely in the implementation of the heuristic processor for which it was conceived