Abstract :
Four topics were discussed: (1) Technology Trends in NBTI: The discussion here centered on how the process technology options can reduce NBTI by optimizing the N,H, and B concentrations at the gate oxide interface. There were some contradicting results which were reported on Deuterium. The group expected that the problem would get worse as scaling continues and we reach the next technology nodes. Looking toward the future, the impact that new, high-k dielectrics will have on NBTI is, unfortunately, not clear at this time. (2) Specifications and Technology Requirements: There is a strong need for a unified specification. Several attendees volunteered to review the JEDEC proposal. A further conclusion was that this unified specification should be general (Idsat, Vtlin, Vtsat, gm, Rout) depending on the application. The group also suggested that a specification for testing conditions is needed. This specification should include relaxation time, extrapolation, and the 2nd slope in stress plots, to name some of these requirements. (3) Design Impact/Optimization of NBTI: Understanding the design impact of NBTI and how to optimize the circuits to minimize NBTI is a strong need in the design community. TcchnologylReliability needs to deliver models to the designer that will answer these issues. The circuit designers must be able to cvaluate the NBTI impact as soon as possible in the design cycle. (4) Device Level Qualification: Device level qualification has been done to estimate the speed impact that NBTI causes on the circuits. But regular BI is not capable of catching NBTI reliability issues. The group suggested that more work is needed to understand the correlation between WLR data and transistor data. The device level qualification work was considered a safety net, and many companies don??t want to do it.
