DocumentCode
2769599
Title
Architecture and Implementation of Attribute Reduction Algorithm Using Binary Discernibility Matrix
Author
Tiwari, K.S. ; Kothari, A.G.
Author_Institution
E&TC Dept., MESCOE, Pune, India
fYear
2011
fDate
7-9 Oct. 2011
Firstpage
212
Lastpage
216
Abstract
In this paper, a rough set processor for robotics applications is proposed. A lot of research work is carried out in implementing the algorithms of rough set theory using various software tools but hardware implementation of them is an area still unexplored. Hardware approach towards this will reduce the computation overhead on the main processor. We have designed and implemented a Binary Discernibility matrix and a Reduct Calculator Block of rough set processor.
Keywords
matrix algebra; microprocessor chips; robots; rough set theory; software tools; attribute reduction algorithm; binary discernibility matrix; computation overhead; reduct calculator block; robotics applications; rough set processor; rough set theory; software tools; Computer architecture; Databases; Hardware; Information systems; Random access memory; Set theory; Software algorithms; Discernibility MATRIX; FPGA; Reduct; Rough set; VHDL;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Intelligence and Communication Networks (CICN), 2011 International Conference on
Conference_Location
Gwalior
Print_ISBN
978-1-4577-2033-8
Type
conf
DOI
10.1109/CICN.2011.42
Filename
6112857
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