A novel flexible foldable systolic architecture FIR filters generator

A novel design tool for flexible implementation of FIR digital Filters on a FPGA is presented. Leveraging a folding systolic architecture, this FIR generation tool is able to offer optimal performance versus chip area trade-offs with different levels of systolic array folding. In this paper, the systolic array design folding theory is presented and applications to FIR design space exploration are discussed. Compared against state of the art FPGA FIR structure, the proposed structure demonstrates clear advantages.