Title :
Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme
Author :
Ren, Yuan ; Gansen, Michael ; Noll, Tobias
Author_Institution :
Dept. of Electr. Eng. & Comput. Syst., RWTH Aachen Univ., Aachen, Germany
Abstract :
To reduce both dynamic and standby power dissipation, a new 6T-based SRAM architecture is proposed. It is partitioned into an optimal number of hierarchical sub-blocks, which are selectively activated by a novel tree address decoder. Also, a new equalizer precharge scheme with reduced leakage paths is presented. Low standby power and stable access are achieved with back-biasing and other techniques. The new approach is verified in a 40-nm CMOS technology by simulation.
Keywords :
CMOS memory circuits; SRAM chips; equalisers; 6T-based SRAM architecture; CMOS technology; dynamic power dissipation; equalizer precharge scheme; hierarchical subblocks; leakage path reduction; low-power 6T-SRAM; size 40 nm; standby power dissipation; tree address decoder; CMOS integrated circuits; CMOS technology; Decoding; Equalizers; Power dissipation; Random access memory; Transistors;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398352
