Implementing image processing algorithms using ‘Hardware in the loop’ approach for Xilinx FPGA

This paper outlines the investigation conducted in fine tuning the performance of our automated surveillance system. The constituent components of the system must have a processing speed of less than 40 ms. This is usually considered to be a standard timing constraint for most automated surveillance systems. To meet this constraint, it is important to quantify the reduction in processing speed that can be achieved if a component of the surveillance system is embedded onto a hardware based platform like an FPGA. A benchmark study was conducted to identify the component that contributed to the longest processing time in the entire system. Once the offending component was identified, its functionality was embedded onto the FPGA board using a combination of MATLAB-Simulink and Xilinx system generator prototyping environment. The results obtained indicated that the processing speed of the component was constantly faster on the FPGA platform as compared to MATLAB or C++ environment.