Title :
Architecture Design of QPP Interleaver for Parallel Turbo Decoding
Author :
Lee, Shuenn-Gi ; Wang, Chung-Hsuan ; Sheen, Wern-Ho
Abstract :
Quadratic permutation polynomial (QPP) interleaver has the advantage of contention-free for parallel memory access and has been adopted in the 3GPP LTE for turbo coding. Conventional implementations of the QPP interleaver based on the look-up table or on-line calculation usually result in large circuit area or higher clock rate for parallel turbo decoding. In this paper, an architecture design of QPP interleaver for parallel turbo decoding is presented which can provide parallel memory access without extra storage of interleaving patterns or the increment of clock rate compared with the conventional approaches. The proposed design is also reconfigurable for variable interleaver lengths.
Keywords :
3G mobile communication; decoding; interleaved codes; parallel memories; polynomials; table lookup; turbo codes; 3GPP LTE; QPP interleaver; architecture design; parallel memory access; parallel turbo decoding; quadratic permutation polynomial; variable interleaver lengths; Chaotic communication; Circuits; Clocks; Delay; Interleaved codes; Iterative decoding; Polynomials; Table lookup; Throughput; Turbo codes;
Conference_Titel :
Vehicular Technology Conference (VTC 2010-Spring), 2010 IEEE 71st
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-2518-1
Electronic_ISBN :
1550-2252
DOI :
10.1109/VETECS.2010.5493793