DocumentCode :
2770590
Title :
Improved Delta Sigma Analog to Digital Converter
Author :
Katara, Arun ; Ramteke, Sandip D. ; Bapat, Abhijit V. ; Jain, Swapnil S.
Author_Institution :
Dept. of Electron. & Telecommun., DMIETR, Wardha, India
fYear :
2011
fDate :
7-9 Oct. 2011
Firstpage :
444
Lastpage :
447
Abstract :
This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time over sampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta- sigma modulators in parallel with no over sampling is similar to operating the same modulator with an over sampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require over sampling.
Keywords :
analogue-digital conversion; delta-sigma modulation; Lth-order delta-sigma modulators; delta sigma analog-to-digital converter; multiple delta-sigma modulators; parallel delta-sigma A/D converter; Delta-sigma modulation; Gain; Modulation; Operational amplifiers; Signal resolution; Simulation; 1 bit D Latch; Analog to Digital converter; Delta-sigma Modulator; comparator;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2011 International Conference on
Conference_Location :
Gwalior
Print_ISBN :
978-1-4577-2033-8
Type :
conf
DOI :
10.1109/CICN.2011.93
Filename :
6112906
Link To Document :
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