Implementation of SHA-2 hash function for a digital signature System-on-Chip in FPGA

The widespread adoption of Internet as a secure medium for communication and e-commerce has made cryptography a vital part of today´s information systems. However, to achieve a more pervasive deployment, the supporting cryptographic (crypto) systems should exhibit processing power of high performance and efficiency. These demanding requirements can be achieved by integrating the cryptosystems into designs based on System-on-Chip (SoC). In this paper, the design and implementation of a crypto hash SHA-2 logic core in reconfigurable hardware is presented. We also discuss a public-key crypto SoC, which uses the SHA-2 hash core in conjunction with a 2048-bit RSA co-processor to perform a digital signature security scheme. We use Verilog to model the hardware, and C to code the embedded software. With the crypto SoC implemented in an Altera Nios II Stratix FPGA-based prototyping system running on a 50 MHz system clock, we obtained a throughput of 644 Mbits/sec for our SHA-512 hardware core.