Low-voltage limitations of memory-rich nano-scale CMOS LSIs

Author

Itoh, Kiyoo ; Horiguchi, Masashi ; Yamaoka, Masanao

Author_Institution

Hitachi, Ltd., Tokyo

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

68

Lastpage

75

Abstract

The low-voltage limitations of memory-rich nano- scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip- flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger V_T variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high- V_DD bulk CMOS LSIs for low-cost low-standby-current applications and low-F_DD FD-SOI LSIs for low-power applications.

Keywords

CMOS digital integrated circuits; DRAM chips; SRAM chips; flip-flops; large scale integration; logic design; logic gates; low-power electronics; silicon-on-insulator; CMOS inverter; DRAM; SRAM; flip-flop circuits; fully-depleted SOI devices; nanoscale CMOS LSI; sense amplifiers; six-transistor cells; size 100 nm; CMOS logic circuits; CMOS memory circuits; CMOS technology; Flip-flops; Inverters; Laboratories; Logic devices; Nanoscale devices; Random access memory; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Conference_Location

Munich

ISSN

1930-8833

Print_ISBN

978-1-4244-1125-2

Type

conf

DOI

10.1109/ESSCIRC.2007.4430250

Filename

4430250