Title :
A Novel on chip LDO voltage regulator in 180nm
Author :
Rao, Patri Sreehari ; Krishnaprasad, K.S.R.
Author_Institution :
Chip Design Center, Nat. Inst. of Technol., Warangal
Abstract :
An on chip low drop out voltage regulator that employs a simple fast path and an elegant compensation scheme is presented in this paper. The novelty in this design is that the device parasitic capacitances are exploited for compensation at different loads. The proposed LDO is designed to provide a constant voltage of 1.2 V and is implemented in UMC 180 nano meter CMOS technology. The voltage regulator presented improves stability even at lighter loads and enhances line and load regulation while providing reasonably good transient response.
Keywords :
CMOS integrated circuits; compensation; transient response; voltage regulators; CMOS technology; compensation scheme; line regulation; load regulation; on chip LDO voltage regulator; size 180 nm; transient response; voltage 1.2 V; CMOS technology; Capacitance; Capacitors; Frequency; Low voltage; Mobile handsets; Poles and zeros; Regulators; Stability; Transient response;
Conference_Titel :
Electronic Design, 2008. ICED 2008. International Conference on
Conference_Location :
Penang
Print_ISBN :
978-1-4244-2315-6
Electronic_ISBN :
978-1-4244-2315-6
DOI :
10.1109/ICED.2008.4786685
