Title :
Design of near threshold All Digital Delay Locked Loops
Author :
Sadi, Mehdi ; Stan, Mircea
Author_Institution :
Electr. & Comput. Eng., Univ. of Virginia Charlottesville, Charlottesville, VA, USA
Abstract :
In this paper we present a detailed methodology for designing ultra low power All Digital Delay Locked Loops (ADDLL) operating at Near Threshold Voltage (NTV). We address the design constraints - increased gate delays, design corner vulnerability and duty cycle mismatch - in scaled Vdd design. Circuit level enhancement techniques are presented to circumvent these issues. We also eliminate the false locking and dithering problems. Finally, based on our methodology, we designed and simulated an ADDLL in a 45nm PDK operating at 0.8-1GHz with 0.5 V supply.
Keywords :
delay lock loops; digital circuits; ADDLL design; NTV; PDK; circuit level enhancement technique; corner vulnerability; duty cycle mismatch; frequency 0.8 GHz to 1 GHz; gate delays; locking-dithering problems; near threshold voltage; near-threshold all-digital delay-locked loop design; size 45 nm; ultralow-power all-digital delay-locked loop design; voltage 0.5 V; Capacitance; Clocks; Delay; Delay lines; Detectors; Inverters; Radiation detectors;
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
Print_ISBN :
978-1-4673-1294-3
DOI :
10.1109/SOCC.2012.6398398
