Impact of stress on various circuit characteristics in 65nm PDSOI technology

Author

Suryagandh, Sushant ; Gupta, Mayank ; Wu, Zhi-Yuan ; Krishnan, Srinath ; Pelella, Mario ; Goo, Jung-Suk ; Thuruthiyil, Ciby ; An, Judy X. ; Chen, Brian Q. ; Subba, Niraj ; Zamudio, Luis ; Yonemura, James ; Icel, Ali B.

Author_Institution

Adv. Micro Devices, Sunnyvale

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

119

Lastpage

122

Abstract

Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.

Keywords

CMOS integrated circuits; integrated circuit modelling; microprocessor chips; silicon-on-insulator; PDSOI technology; advanced CMOS technologies; analog behavior; circuit blocks; circuit characteristics; hysteresis; logic performance; microprocessor chip; noise properties; size 65 nm; stress optimization; Analog circuits; CMOS logic circuits; CMOS technology; Circuit noise; Delay; Germanium silicon alloys; Hysteresis; MOSFETs; Silicon germanium; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Conference_Location

Munich

ISSN

1930-8833

Print_ISBN

978-1-4244-1125-2

Type

conf

DOI

10.1109/ESSCIRC.2007.4430260

Filename

4430260