Efficient crosstalk estimation and reduction in high speed designs

With rapid advances in VLSI, technology has enabled us to reduce the minimum feature sizes of sub-quarter microns and the switching times to tens of picoseconds or even less. The trend in VLSI industry is moving toward designs that are more complex, higher operating frequencies, sharper rise times, shrinking device sizes and low power consumption. Although the device noise sources (i.e. shot noise, flicker noise, thermal noise) are still not an issue in the performance of digital circuits, external noise sources (i.e. crosstalk, power/ground bounce, substrate noise) significantly degrade the performance and the reliability of digital integrated circuits. These external noise sources are mostly due to the fact that on-chip interconnects act like transmission lines and that the neighboring wires exert electric and magnetic couplings on each other. Among the various external noise sources, problems related to the on-chip capacitive crosstalk are particularly important. Because the thickness of the wires is not scaled down by as much as the width of the wires and because the wires are packed ever closer to each other, the inter-wire coupling capacitances become larger, the ratio between the coupling capacitance and the total capacitance increases, and as a result the capacitive coupling noise increases[6].High-speed digital circuits heavily use the dynamic logic family. Dynamic circuits with their two phases of operations are more susceptible to this kind of noise compared to the static logic.