A novel technique for speeding up domino CMOS circuits containing a long chain of NMOS transistors

Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, for wide fan in domino logic, that is when there is a long chain of NMOS transistors (typically 8 or more) connected in series in the pull-down network (PDN), the discharging of the dynamic-node capacitor becomes very slow in case all the inputs are activated during the evaluation phase. The larger the fan in, the slower the circuit will be. So, speeding up the operation for this input combination will be of paramount importance. In this paper, we propose a novel technique for speeding up the performance of such circuits using a current mirror for discharging the dynamic-node capacitor through two branches instead of one. A compact from for the discharging time delay of the dynamic-node capacitor through a chain of NMOS transistors with and without the current mirror added will be derived. The current-mirroring ratio should lie within a specified range; a mathematical procedure for finding this range will be presented in this paper. The proposed technique was simulated for the 0.13 mum technology with V_DD=1.2 V. Simulation results show that the discharging time delay decreases from 500 ps to 400 ps using a current mirror with a current-mirroring ratio of 5. Also, the power consumption decreases and the noise margin improves due to the inhibition of the keeper contention current.