• DocumentCode
    2771450
  • Title

    A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems

  • Author

    Nam, Byeong-Gyu ; Yoo, Hoi-Jun

  • Author_Institution
    Korea Adv. Inst. of Sci. & Technol., Daejeon
  • fYear
    2007
  • fDate
    11-13 Sept. 2007
  • Firstpage
    232
  • Lastpage
    235
  • Abstract
    A low-power, high-performance 4-way 32-bit vector processor is developed for handheld 3D graphics systems. It contains a floating-point unified matrix, vector, and elementary function unit. By utilizing the logarithmic arithmetic, the unit achieves single-cycle throughput for all these operations except for the matrix-vector multiplication with 2-cycle throughput. The processor featured by this function unit, cascaded integer-float datapath, reconfiguration of datapath, operand forwarding in logarithmic domain, and vertex cache takes 9.7 mm2 in 0.18 mum CMOS technology and achieves 141 Mvertices/s for geometry transformation and 12.1 Mvertices/s for OpenGL transformation and lighting at 200 MHz with 86.6 mW power consumption.
  • Keywords
    CMOS integrated circuits; computer graphic equipment; floating point arithmetic; matrix algebra; 2-cycle throughput; CMOS technology; cascaded integer-float datapath; datapath reconfiguration; elementary function unit; floating-point unified matrix; handheld 3D graphics systems; logarithmic arithmetic; low-power vector processor; matrix-vector multiplication; single-cycle throughput; Arithmetic; CMOS technology; Delay; Geometry; Graphics; Piecewise linear approximation; Pipelines; Table lookup; Throughput; Vector processors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
  • Conference_Location
    Munich
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4244-1125-2
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2007.4430286
  • Filename
    4430286