Title :
Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW
Author :
Galdi, I. ; Bonizzoni, E. ; Maloberti, F. ; Manganaro, G. ; Malcovati, P.
Author_Institution :
Univ. of Pavia, Pavia
Abstract :
A band-pass SigmaDelta modulator that uses two time interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40-MHz IF provide a signal band of 1 MHz with 72-dB DR and 65.1-dB peak SNR. The circuit, integrated in a 0.18-mum CMOS technology, uses a 60-MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 dBc. The power consumption is 16 mW with 1.8-V supply.
Keywords :
CMOS integrated circuits; poles and zeros; sigma-delta modulation; SigmaDelta modulator; band-pass sigma-delta modulator; bandwidth 1 MHz; cross-coupled paths; frequency 40 MHz; frequency 60 MHz; power 16 mW; size 0.18 mum; time interleaved second-order modulators; voltage 1.8 V; Bandwidth; CMOS technology; Circuits; Clocks; Energy consumption; Frequency; Noise shaping; Sampling methods; Signal synthesis; Transfer functions;
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1125-2
DOI :
10.1109/ESSCIRC.2007.4430290
