Title :
A highly scalable 2-bit asymmetric double-gate MOSFET nonvolatile memory
Author :
Yuen, Kam Hung ; Man, Tsz Yin ; Chan, Mansun
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
A Metal Oxide Nitride Oxide Semiconductor (MONOS) Asymmetric Double Gate (ADG) Nonvolatile Memory (NVM) cell is proposed. In addition to the improved scalability of the NVM cell made possible by the double-gate structure, the 2 conducting channels also provide a 2-bit per cell storage mechanism. The scalability of the device down to 50 nm is demonstrated by numerical simulation. The operation mechanisms including read, program and erase in an array structure are also studied and described in this paper.
Keywords :
MOS memory circuits; MOSFET; NOR circuits; elemental semiconductors; flash memories; integrated circuit modelling; programmable logic arrays; random-access storage; semiconductor thin films; silicon; 2 bit; 2-bit per cell storage mechanism; 50 nm; Si; array structure; conducting channels; erasing operation; highly scalable 2-bit asymmetric double-gate MOSFET nonvolatile memory; metal oxide nitride oxide semiconductor asymmetric double gate nonvolatile memory cell; numerical simulation; programming; reading operation; CMOS technology; Dielectrics; Flash memory; MONOS devices; MOSFET circuits; Nonvolatile memory; Numerical simulation; Scalability; Silicon; Tunneling;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN :
0-7803-7749-4
DOI :
10.1109/EDSSC.2003.1283483
