A method for a priori implementation effort estimation for hardware design

This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of independent paths of its algorithms. We define a metric which exploits the relation between the number of independent paths in an algorithm and the corresponding implementation effort. Furthermore, we complement the metric with a correction function taking the designer´s experience into account. Our experimental results show that with the proposed approach it is possible to estimate the hardware implementation effort, and thereby facilitating designers and managers needs for estimating the time-to-market schedule.