Title :
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS
Author :
Agarwal, Amit ; Banerjee, Nilanjan ; Hsu, Steven K. ; Krishnamurthy, Ram K. ; Roy, Kaushik
Author_Institution :
Intel Corp., Hillsboro
Abstract :
This paper describes a 48times42b 1-read, 1-write ported register file which operates at supply voltage range of 1.2 V (6.1-6.3 GHz, 47 mW) down to 0.2 V (4-4.4 MHz, 0.01 mW) in 65 nm CMOS. Two programmable techniques, triple stacking and forced stacking are proposed which enable register files to operate at ultra low supply voltages while maintaining the performance comparable to conventional design at high supply voltages.
Keywords :
CMOS integrated circuits; MMIC; UHF integrated circuits; programmable circuits; CMOS; forced stacking; frequency 4.4 MHz to 6.3 GHz; programmable register file; size 65 nm; triple stacking; voltage 200 mV to 1.2 V; voltage supply; Circuits; Degradation; Delay; Dynamic voltage scaling; Leakage current; Low voltage; MOS devices; Noise figure; Registers; Stacking;
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
Print_ISBN :
978-1-4244-1125-2
DOI :
10.1109/ESSCIRC.2007.4430307
