Novel principle and realization of simple low-power low-noise correlated double sampling for CMOS pixel readout circuit

The CDS technique is the traditional approach used to reduce the readout noise of CMOS APS. The conventional CDS circuit has many disadvantages, such as the additional noise after CDS circuit, the large imager size and the big power dissipation due to a large number of transistors used. In this paper a reduced-area, low-power and low-noise CDS circuit for CMOS APS has been proposed. For one spur track of the conventional CDS has saved and the low-power SEDP is used to finish the difference and amplified function, the area of the pixel cell with proposed CDS is reduced by a factor of above 2.5. The hspice simulation results show that the power dissipation of the pixel cell with proposed CDS is 73.96 μW and the total output noise voltage of the pixel cell with the CDS circuit is 0.887 μV/√(Hz) based on the tsmc 0.6 μm technology.