DocumentCode :
2771936
Title :
80 GHz low noise amplifiers in 65nm CMOS SOI
Author :
Martineau, Baudouin ; Cathelin, Andreia ; Danneville, François ; Kaiser, Andreas ; Dambrine, Gilles ; Lepilliet, Sylvie ; Gianesello, Frederic ; Belot, Didier
Author_Institution :
FTM, Grenoble
fYear :
2007
fDate :
11-13 Sept. 2007
Firstpage :
348
Lastpage :
351
Abstract :
A 1 stage and 3 stages 80 GHz low noise amplifiers (LNA) are presented in this paper. Both mm-wave LNA are integrated in a 65 nm CMOS SOI process. The one stage amplifier exhibits 2.1 dB gain and a noise figure of 4.5 dB at 80 GHz. The input and output return losses are -13 dB and -6 dB respectively. This amplifier consumes 22 mW from a supply voltage of 1.2 V and occupies an area of 0.64 mm2 including the pads. The 3 stages LNA presents a gain of 7.2 dB and a noise figure of 5.7 dB at 80 GHz with an input and output matching better than -14 dB and -10 dB respectively. The 3 stages amplifier consumes 70 mW from a supply voltage of 1V and occupies an area of 0.98 mm2 including pads.
Keywords :
CMOS integrated circuits; low noise amplifiers; millimetre wave amplifiers; silicon-on-insulator; CMOS process; SOI process; frequency 80 GHz; gain 2.1 dB; gain 7.2 dB; low noise amplifiers; millimeter wave LNA; noise figure 4.5 dB; noise figure 5.7 dB; power 22 mW; power 70 mW; size 65 nm; voltage 1 V; voltage 1.2 V; CMOS process; CMOS technology; Conductivity; Coplanar waveguides; Frequency; Low-noise amplifiers; MOSFET circuits; Noise figure; Parasitic capacitance; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location :
Munich
ISSN :
1930-8833
Print_ISBN :
978-1-4244-1125-2
Type :
conf
DOI :
10.1109/ESSCIRC.2007.4430315
Filename :
4430315
Link To Document :
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