Statistical modeling for the minimum standby supply voltage of a full SRAM array

This paper presents two fast and accurate methods to estimate the lower bound of supply voltage scaling for standby SRAM/cache leakage power reduction of an SRAM array. The data retention voltage (DRV) defines the minimum supply voltage for a cell to hold its state. Within-die variation causes a statistical distribution of DRV for individual cells in a memory array, and cells far out the tail (i.e. >6sigma) limit the array DRV for large memories. We present two statistical methods to estimate the tail of the DRV distribution. First, we develop a new statistical model based on the connection between DRV and static noise margin (SNM). Second, we apply our Statistical Blockade tool to obtain fast Monte-Carlo simulation and a generalized Pareto distribution (GPD) model for comparison. Both the new model and the GPD model offer a high accuracy (<2% error) and a huge speed-up (>10⁴times for 1 G-b memory) over Monte-Carlo simulation. In addition, both models show a very close agreement with each other at the tail even beyond 7sigma.