DocumentCode :
2772146
Title :
Adaptive Power Optimization of On-chip SNUCA Cache on Tiled Chip Multicore Architecture Using Remap Policy
Author :
Dani, Aparna Mandke ; Amrutur, Bharadwaj ; Srikant, Y.N.
Author_Institution :
Indian Inst. of Sci., Bangalore, India
fYear :
2011
fDate :
26-27 Oct. 2011
Firstpage :
12
Lastpage :
17
Abstract :
Advances in technology have increased the number of cores and size of caches present on chip multicore platforms(CMPs). As a result, leakage power consumption of on-chip caches has already become a major power consuming component of the memory subsystem. We propose to reduce leakage power consumption in static nonuniform cache architecture(SNUCA) on a tiled CMP by dynamically varying the number of cache slices used and switching off unused cache slices. A cache slice in a tile includes all cache banks present in that tile. Switched-off cache slices are remapped considering the communication costs to reduce cache usage with minimal impact on execution time. This saves leakage power consumption in switched-off L2 cache slices. On an average, there map policy achieves 41% and 49% higher EDP savings compared to static and dynamic NUCA (DNUCA) cache policies on a scalable tiled CMP, respectively.
Keywords :
cache storage; microprocessor chips; multiprocessing systems; power aware computing; power consumption; Remap policy; adaptive power optimization; cache bank; cache slice; leakage power consumption; memory subsystem; on-chip SNUCA cache; static nonuniform cache architecture; tiled chip multicore architecture; Clocks; Instruction sets; Monitoring; Power demand; Switches; System-on-a-chip; Tiles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Architecture and Multi-Core Applications (WAMCA), 2011 Second Workshop on
Conference_Location :
Vitoria, Espirito Santo
Print_ISBN :
978-1-4673-0221-0
Type :
conf
DOI :
10.1109/WAMCA.2011.14
Filename :
6112994
Link To Document :
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