A 7-μW clock generator in 0.18-μm CMOS for passive UHF RFID EPC G2 tags

An ultra-low-power clock generator for passive UHF RFID tag is implemented in 0.18-mum CMOS process. By using the technique of dual-path clock generation with multiple clock rates and multiple supply voltages, clock accuracy is much improved and power consumption is reduced. Under the injection-locked condition, the measured cycle-to-cycle jitter of the clock generator is 23.7 ps and the peak-to-peak value is 164 ps with an input at 900 MHz and an output at 3.5 MHz. The overall power consumption is only 7 muW and the core chip area is 0.02 mm².