DocumentCode :
2772233
Title :
[Title page i]
fYear :
2011
fDate :
26-27 Oct. 2011
Abstract :
The following topics are dealt with: large scale Kronecker product; supercomputers; trace-based visualization; on-chip SNUCA cache; tiled chip multicore architecture; process mapping; network-on-chip; and economical two-fold working precision matrix multiplication.
Keywords :
cache storage; data visualisation; matrix multiplication; multiprocessing systems; network-on-chip; parallel architectures; parallel machines; economical two-fold working precision matrix multiplication; large scale Kronecker product; network-on-chip; on-chip SNUCA cache; process mapping; supercomputers; tiled chip multicore architecture; trace-based visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Architecture and Multi-Core Applications (WAMCA), 2011 Second Workshop on
Conference_Location :
Vitoria, Espirito Santo
Print_ISBN :
978-1-4673-0221-0
Type :
conf
DOI :
10.1109/WAMCA.2011.1
Filename :
6112999
Link To Document :
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