ASIC modeling and simulation of adaptive FIR filter

When designing VLSI systems, it is important to have a systematic approach so that the design can be done timely and efficiently, which ultimately leads to lower cost. Apart from this, for an ASIC design to be completed successfully from specification to tape out, it is imperative that a particular process be defined and followed. The work in this paper presents ASIC design flow for the implementation of adaptive FIR filter using MATLAB and Mentor Graphics IC design tools. Algorithm modeling is initially performed to obtain suitable parameters of the adaptive FIR filter, followed by RTL design using VHDL, ASIC synthesis to TSMC 0.25 mum process technology, physical modeling using schematic driven layout, parasitic extraction, and verification at every design steps. The adaptive FIR filter is designed using 17, 654 transistors with core cell area of 0.562 mm², and performance suitable for current and next generation mobile communication applications.