A fail-safe ASIC for implantable neural stimulation

We implemented a stimulator output stage that is failsafe without the need for off-chip blocking capacitors. Both the system architecture and details on the key circuits are described. The novel design employs high-frequency current-switching, a fully isolated bridge rectifier core, and AC-coupled discharging for the stimulation load. The prototype circuit was fabricated in a 1-mum silicon-on-insulator CMOS technology and operates from a power supply between the range of 5 V to 18 V, depending on the stimulation load and the stimulus current amplitude. Miniaturization of the entire stimulator output stage into a single fail-safe ASIC, is a major advance towards developing neural stimulators for multi-functional restoration after spinal cord injury.