DocumentCode
2772339
Title
Stability analysis of a 400 mV 4-transistor CMOS-SOI SRAM cell operated in subthreshold
Author
Thomas, Olivier ; Amara, Amara ; Vladimirescu, Andrei
Author_Institution
ISEP, Paris, France
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
247
Lastpage
250
Abstract
This paper addresses the design robustness of CMOS SOI memory cells operating at Ultra-Low-Voltage, ULV. An analytical approach to the stability problem of SRAM cells is presented. The analysis is performed for a 6-transistor and 4-transistor CMOS SOI memory cell based on an analytical subthreshold estimation model.
Keywords
CMOS integrated circuits; CMOS memory circuits; MOSFET; SRAM chips; elemental semiconductors; semiconductor device models; silicon-on-insulator; 400 mV; Si; robustness; stability analysis; transistor CMOS-SOI SRAM memory cell; CMOS logic circuits; Handheld computers; Performance analysis; Pervasive computing; Portable computers; Random access memory; Semiconductor device modeling; Silicon on insulator technology; Stability analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283524
Filename
1283524
Link To Document