DocumentCode
2772457
Title
Clock gater standard cell design
Author
Hong, LUI Siu ; Wong, Alfred K.
Author_Institution
Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
fYear
2003
fDate
16-18 Dec. 2003
Firstpage
273
Lastpage
276
Abstract
This paper presents a new design of a clock gater standard cell. The circuits are designed and laid out according to the TSMC 250-nm, 2.5 V process. By using a differential latch rather than a transmission gate latch in the circuit, the layout area can be reduced by 20%. Computer simulation including parasitics shows that there is also a reduction in power consumption, the percentage decrease depends on the enable signal activity factor.
Keywords
CMOS logic circuits; clocks; digital simulation; flip-flops; integrated circuit layout; power consumption; 2.5 V; 250 nm; clock gater standard cell; computer simulation; differential latch; power consumption; signal activity factor; transmission gate latch; Capacitance; Circuit synthesis; Clocks; Digital signal processing; Energy consumption; Latches; Network synthesis; Portable computers; Signal design; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2003 IEEE Conference on
Print_ISBN
0-7803-7749-4
Type
conf
DOI
10.1109/EDSSC.2003.1283530
Filename
1283530
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