Noise-aware domino logic design for deep submicron technology

In this paper, we describe split-path domino (SP domino) logic which exhibits high-speed operation due to halved charge sharing problem. SP domino logic splits NMOS stacked transistors use for logic evaluation, in order to reduce charge sharing problem, which has become one of the critical noise problem in VDSM technology. Furthermore, SP domino logic needs no signal ordering, which simplifies logic synthesis. Our experimental results on several logic gates using 0.18 μm CMOS technology showed that proposed logic improves performance over textbook domino circuit up to 17% under the same noisy environment. Hence, SP domino logic is a good candidate for high-speed low-voltage operation in a very noisy environment.