A Greedy Heuristic for Process Mapping on Networks-on-Chip

Author

Oliveira, Poliana A C ; Avelar, Cíntia P. ; Guimarães, Silvio Jamil F ; Freitas, Henrique C.

Author_Institution

Dept. de Cienc. da Comput., Pontificia Univ. Catolica de Minas Gerais (PUC Minas), Belo Horizonte, Brazil

fYear

2011

fDate

26-29 Oct. 2011

Firstpage

4

Lastpage

4

Abstract

The state-of-the-art related to many-core processors focuses on Networks-on-Chip (NoCs) as approach to provide on-chip message-passing communication. The main problem is the number of hops from source to destination increasing the latency to exchange data based on network packets. Our goal is to propose a greedy heuristic for process mapping on NoCs clustering processes that have more communication on nearest cores. The evaluation method is based on simulation of parallel workloads on a NoC. The greedy heuristic achieves a higher throughput (up to 23.04%) and lower energy consumption (up to 9.87%) than a direct mapping approach for most workloads.

Keywords

greedy algorithms; message passing; multiprocessing systems; network-on-chip; NoC clustering processes; data exchange latency; greedy heuristic; network packets; networks-on-chip; on-chip message-passing communication; process mapping; Energy consumption; Program processors; System-on-a-chip; Throughput; Greedy Heuristic; Network-on-Chip; Parallel Workloads; Process Mapping;

fLanguage

English

Publisher

ieee

Conference_Titel

Sistemas Computacionais (WSCAD-SSC), 2011 Simpasio em

Conference_Location

Vitoria

Print_ISBN

978-1-4673-0303-3

Type

conf

DOI

10.1109/WSCAD-SSC.2011.16

Filename

6113016