DocumentCode
2772498
Title
An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS
Author
Li, Lijun ; Green, Michael
Author_Institution
Univ. of California, Irvine
fYear
2007
fDate
11-13 Sept. 2007
Firstpage
508
Lastpage
511
Abstract
An 11.75-Gb/s combined DFE and CDR circuit in 0.18mum CMOS is presented. The feedback path of the DFE is merged with an Alexander phase detector resulting in reduced power and enhanced performance. It is capable of equalizing copper cable channels with up to 12dB loss at 5.875GHz Nyquist frequency and consumes 201mW with a 1.8 supply voltage.
Keywords
CMOS integrated circuits; decision feedback equalisers; mixed analogue-digital integrated circuits; phase detectors; synchronisation; Alexander phase detector; CMOS; bit rate 11.75 Gbit/s; clock data recovery; combined decision feedback equalizer; copper cable channel; power 201 mW; size 0.18 mum; voltage 1.8 V; Adders; Clocks; Copper; Decision feedback equalizers; Detectors; Feedback circuits; Intersymbol interference; Phase detection; Signal generators; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European
Conference_Location
Munich
ISSN
1930-8833
Print_ISBN
978-1-4244-1125-2
Type
conf
DOI
10.1109/ESSCIRC.2007.4430353
Filename
4430353
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