Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions

The failure of power DMOS transistor arrays under unclamped inductive switching- (UIS-) stress conditions is investigated using continuous field-based electrothermal device simulation. With reference to previous work of the authors, progressively deeper insight into the failure mechanism enables its detailed understanding. The temperature and current distributions among parallel DMOS cells in the array indicate that indeed the simulation of one single cell can be used as a reliable means of assessing the safe operating area (SOA) of the transistor array under UIS stress conditions. A comparison with measured data shows reasonable agreement with the simulation results and, thus, corroborates the validity of our model.