An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization

Author

Saif, S.M. ; Abbas, Hazem M. ; Nassar, S.M.

Author_Institution

Mentor Graphics Corp., Cairo

fYear

0

fDate

0-0 0

Firstpage

2815

Lastpage

2822

Abstract

This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.

Keywords

Hopfield neural nets; field programmable gate arrays; image colour analysis; image enhancement; image sequences; video signal processing; Xilinx Virtex-E; algorithm-to-architecture mapping; competitive Hopfield neural network; field programmable gate array; gray-level scale; hardware implementation; image enhancement; image histogram equalization; video sequence; Discrete cosine transforms; Field programmable gate arrays; Hardware; Helium; Histograms; Hopfield neural networks; Image processing; Intelligent networks; Pixel; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 2006. IJCNN '06. International Joint Conference on

Conference_Location

Vancouver, BC

Print_ISBN

0-7803-9490-9

Type

conf

DOI

10.1109/IJCNN.2006.247189

Filename

1716479