Neural Network Based Memory Access Prediction Support for SoC Dynamic Reconfiguration

The introduction of embedded processors into field programmable gate arrays (FPGA) allows the implementation of a new type of systems on chip (SOC) designs which are the hardware/software designs programmable systems. Such embedded systems are usually running under hard real time constraints. Hardware and software components included in such systems exhibit variability and therefore affect execution time. The major reason of this variability in the software components is the cache miss operation. Indeed, a cache memory access from an embedded microprocessor might result in a cache hit if the data is available or a cache miss so the data need to be fetched with an additional delay from an external memory. It is therefore highly desirable to predict future memory accesses during execution in order to appropriately evaluate the design performance. The prediction of all component´s design performances allow us to implement an efficient management strategy based on dynamic reconfigurable devices. In this paper, we also evaluate the potential of several artificial neural networks for the prediction of instruction memory addresses allocated by an embedded processor. Neural networks have the potential to solve the non-linear behavior observed in memory accesses during program execution. However, embedded processors execute millions of instructions and therefore millions of addresses to be predicted. This very challenging problem of neural network based prediction of large time series is approached in this paper by evaluating various neural network architectures based on the recurrent neural network paradigm with pre-processing stage based on the self organizing map (SOM) classification technique.